drm/msm/registers: Fix encoding fields in 64b registers

drm/msm/registers: Fix encoding fields in 64b registers

Based on mesa commit 3f70b0578402 ("freedreno/registers: Fix encoding
fields in 64b registers"), but with some fixes to not skip emitting
interrupt enum values.

v2: Don't append "ull" to 32b reg MASK defines, to avoid printf format
    conversion warnings all over the place

Co-developed-by: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689141/
Message-ID: <20251118152952.226510-1-robin.clark@oss.qualcomm.com>