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PCI: dwc: Add register and bitfield definitions
authorVincent Guittot <vincent.guittot@linaro.org>
Fri, 21 Nov 2025 16:49:18 +0000 (17:49 +0100)
committerBjorn Helgaas <bhelgaas@google.com>
Tue, 2 Dec 2025 20:03:11 +0000 (14:03 -0600)
commit045ad2c623d607f2c7720e2b8fcda675d96f7381
tree3bb2a4ebf5bc3e92d6b2cf205ffe2c417511acc8tree | snapshot
parent0472132df8489c56ae446646214f3cb2b7cd3946commit | diff
PCI: dwc: Add register and bitfield definitions

Add register and bitfield definitions:

  - GEN3_RELATED_OFF_EQ_PHASE_2_3 field of GEN3_RELATED_OFF

  - Coherency control registers

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251121164920.2008569-3-vincent.guittot@linaro.org
drivers/pci/controller/dwc/pcie-designware.h diff | blob | blame | history
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