]> Gentwo Git Trees - linux/.git/commit
net/mlx5: Add balance ID support for LAG multiplane groups
authorMark Bloch <mbloch@nvidia.com>
Thu, 23 Oct 2025 09:17:00 +0000 (12:17 +0300)
committerPaolo Abeni <pabeni@redhat.com>
Tue, 28 Oct 2025 10:11:27 +0000 (11:11 +0100)
commit20d78ead947783b039b02ca4b8c551b4d1894759
treed127c6b6d85b9addfd6dc8370a56894080a3e92e
parent075e85a1261e4653c2068e68a8c91da6c7bc4e60
net/mlx5: Add balance ID support for LAG multiplane groups

Implement balance ID support for multiplane LAG configurations. This
feature enables per-multiplane group load balancing by extending the
software system image GUID with a balance ID component.

Key implementations:
- Enable lag_per_mp_group capability when supported by hardware.
- Append load_balance_id to software system image GUID when conditions
  are met.
- Increase MLX5_SW_IMAGE_GUID_MAX_BYTES from 8 to 9 to accommodate the
  extra byte.

The balance ID is appended to the system image GUID only when both
load_balance_id and lag_per_mp_group capabilities are available, ensuring
backward compatibility while enabling enhanced LAG functionality.

This enhancement allows for more granular load balancing control in complex
multi-plane LAG deployments, improving network performance and flexibility.

Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Reviewed-by: Shay Drori <shayd@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1761211020-925651-6-git-send-email-tariqt@nvidia.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
drivers/net/ethernet/mellanox/mlx5/core/main.c
drivers/net/ethernet/mellanox/mlx5/core/vport.c
include/linux/mlx5/driver.h