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(parent: cca7c08) | patch
drm/i915/tc: Cache the pin assignment value
authorImre Deak <imre.deak@intel.com>
Tue, 5 Aug 2025 07:36:59 +0000 (10:36 +0300)
committerImre Deak <imre.deak@intel.com>
Wed, 13 Aug 2025 12:03:29 +0000 (15:03 +0300)
commit24d1cdacac11ddc3388714c5f82d31a480659ac7
treeb2059fe12100a446e7c1fb8aa071ca1b673d8cc6tree | snapshot
parentcca7c083a3f622164a3615ed243e6a5ccdd1dd10commit | diff
drm/i915/tc: Cache the pin assignment value

Cache the pin assignment value. This is more consistent with the way the
max lane count value is tracked and a bit more efficient than reading
out the same value from HW each time it's queried.

Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250805073700.642107-19-imre.deak@intel.com
Signed-off-by: Imre Deak <imre.deak@intel.com>
drivers/gpu/drm/i915/display/intel_tc.c diff | blob | blame | history
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