]> Gentwo Git Trees - linux/.git/commit
Merge tag 'zynqmp-dt-for-6.14' of https://github.com/Xilinx/linux-xlnx into soc/dt
authorArnd Bergmann <arnd@arndb.de>
Wed, 19 Mar 2025 20:45:35 +0000 (21:45 +0100)
committerArnd Bergmann <arnd@arndb.de>
Wed, 19 Mar 2025 20:45:36 +0000 (21:45 +0100)
commit32e0c5fe6e8bfd31220f0b7921481f0e5fb6055b
treee99a60b846cb5554e086686a993f5a83b7d7725c
parent877fb9a3ca78e01c194d3671c12b466690a3dc87
parentf0ceedd52a69a8bf63778b1fe9e1c10e02ecd3fd
Merge tag 'zynqmp-dt-for-6.14' of https://github.com/Xilinx/linux-xlnx into soc/dt

arm64: ZynqMP DT changes for 6.15

- Align clock nodes with DT binding
- Add the first VN-X Versal NET board
- Move constants out of DT bindings

* tag 'zynqmp-dt-for-6.14' of https://github.com/Xilinx/linux-xlnx:
  dt-bindings: xilinx: Deprecate header with firmware constants
  arm64: zynqmp: Use DT header for firmware constants
  arm64: versal-net: Add description for b2197-00 revA board
  dt-bindings: soc: Add new VN-X board description based on Versal NET
  arm64: zynqmp: add clock-output-names property in clock nodes

Link: https://lore.kernel.org/r/CAHTX3d+u1VmxP4vm0peQS-ST7o0BuCpKUPRVCSLMfAAb=eV3Xg@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>