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clk: ast2600: Add RMII RCLK gates for all four MACs
authorAndrew Jeffery <andrew@aj.id.au>
Thu, 10 Oct 2019 02:07:25 +0000 (12:37 +1030)
committerStephen Boyd <sboyd@kernel.org>
Fri, 8 Nov 2019 16:48:41 +0000 (08:48 -0800)
commit3696eebd810cf084b3662d3c3b85cd84b61090f3
treec948172d8bd4687a297837c14d97c04edbd13759tree | snapshot
parent309d673e9596f9706e72615583f2f689cf3fbfb5commit | diff
clk: ast2600: Add RMII RCLK gates for all four MACs

RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a
single gate for each MAC.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lkml.kernel.org/r/20191010020725.3990-3-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/clk-ast2600.c diff | blob | blame | history
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