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EDAC/skx_common: Extend the maximum number of DRAM chip row bits
authorQiuxu Zhuo <qiuxu.zhuo@intel.com>
Wed, 19 Nov 2025 20:11:40 +0000 (12:11 -0800)
committerTony Luck <tony.luck@intel.com>
Fri, 21 Nov 2025 18:20:51 +0000 (10:20 -0800)
commit39abdcbdad597b1ac3dabd44a757de91b87c683a
tree508fe824de3e9ac3ebb2a992da84cf3b32d3e277tree | snapshot
parent9fc67b11703fe9d8a5617ccacec2a452e455fa52commit | diff
EDAC/skx_common: Extend the maximum number of DRAM chip row bits

The allowed maximum number of row bits for DRAM chips in the Diamond
Rapids server processor is up to 19. Extend the current maximum row
bits from 18 to 19.

Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://patch.msgid.link/20251119134132.2389472-6-qiuxu.zhuo@intel.com
drivers/edac/skx_common.c diff | blob | blame | history
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