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drm/msm/dsi/phy: Define PHY_CMN_CTRL_0 bitfields
authorKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tue, 10 Jun 2025 14:05:45 +0000 (16:05 +0200)
committerDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Tue, 2 Sep 2025 14:00:57 +0000 (17:00 +0300)
commit3bb6433ecb65ab91862e39a9a788beecd38e10de
tree6b53cf862274983d5ca142c49b0286d746fd0967tree | snapshot
parentb63f008f395ca5f6bc89123db97440bdc19981c4commit | diff
drm/msm/dsi/phy: Define PHY_CMN_CTRL_0 bitfields

Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
masks and shifts and make the code a bit more readable.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/657818/
Link: https://lore.kernel.org/r/20250610-b4-sm8750-display-v6-7-ee633e3ddbff@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c diff | blob | blame | history
drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml diff | blob | blame | history
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