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clk: tegra: change post IDDQ release delay to 5us
authorPeter De Schrijver <pdeschrijver@nvidia.com>
Tue, 25 Jul 2017 10:34:09 +0000 (13:34 +0300)
committerStephen Boyd <sboyd@codeaurora.org>
Wed, 23 Aug 2017 22:59:42 +0000 (15:59 -0700)
commit3dd065e70e6c6ec54d2fc7d5158d88518d3c5ab9
tree7238546e60d8885941db92b5b70f3196aa503587tree | snapshot
parent82c875ca2b26fcca1a92ed4fd3a10bd653d6f680commit | diff
clk: tegra: change post IDDQ release delay to 5us

Increase delay after PLL IDDQ release to 5us per PLL specifications.

based on work by Alex Frid <afrid@nvidia.com>

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/tegra/clk-pll.c diff | blob | blame | history
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