]> Gentwo Git Trees - linux/.git/commit
gentwo / linux / .git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 6e5aee0) | patch
MIPS: mipsmtregs: Fix target register for MFTC0
authorJiaxun Yang <jiaxun.yang@flygoat.com>
Sun, 16 Jun 2024 13:25:02 +0000 (14:25 +0100)
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>
Fri, 21 Jun 2024 08:16:15 +0000 (10:16 +0200)
commit4a3e37b3caea817199757a0b13aa53dd7c9376c8
treeba80f3bcbec42697249e963aff884ae3d6a49230tree | snapshot
parent6e5aee08bd2517397c9572243a816664f2ead547commit | diff
MIPS: mipsmtregs: Fix target register for MFTC0

Target register of mftc0 should be __res instead of $1, this is
a leftover from old .insn code.

Fixes: dd6d29a61489 ("MIPS: Implement microMIPS MT ASE helpers")
Cc: stable@vger.kernel.org
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
arch/mips/include/asm/mipsmtregs.h diff | blob | blame | history
Development tree.