]> Gentwo Git Trees - linux/.git/commit
clk: renesas: r9a07g044: Add MSTOP for RZ/G2L
authorClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Wed, 6 Aug 2025 09:21:27 +0000 (12:21 +0300)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 20 Aug 2025 07:16:32 +0000 (09:16 +0200)
commit56de5e305d4ba25eed5740b338f7ecb8cf342aa6
tree4c4fff87fd373d56812bd1c7d7da2acc891625cf
parentf0cb3463d0244765ab66792a88dc5e2152c130e1
clk: renesas: r9a07g044: Add MSTOP for RZ/G2L

Add MSTOP configuration for all the module clocks on the RZ/G2L
based SoCs (RZ/G2L, RZ/G2LC, RZ/V2L).

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806092129.621194-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c
drivers/clk/renesas/rzg2l-cpg.h