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dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI
authorJunhui Liu <junhui.liu@pigmoral.tech>
Tue, 21 Oct 2025 09:41:40 +0000 (17:41 +0800)
committerThomas Gleixner <tglx@linutronix.de>
Tue, 11 Nov 2025 21:17:21 +0000 (22:17 +0100)
commit579951da64253e9592d21e54b1535e0119df78ab
tree3ef875122f813fd5ac35123efa07df40cf959bc4tree | snapshot
parentb90ac5fe3285aa8bed625375d1df959c4c9a2cdbcommit | diff
dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI

Add MSWI support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a
TIMER unit compliant with the ACLINT specification.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251021-dr1v90-basic-dt-v3-5-5478db4f664a@pigmoral.tech
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml diff | blob | blame | history
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