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(parent: dcf1018) | patch
drm/i915/display: Add power well mapping for WCL
authorChaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Fri, 8 Aug 2025 08:19:30 +0000 (13:49 +0530)
committerGustavo Sousa <gustavo.sousa@intel.com>
Wed, 13 Aug 2025 14:13:02 +0000 (11:13 -0300)
commit9465dd7c400d47439d3446de5b3f1ecfb5ea1bc6
tree8c14672b4834a1c84b2b591cec1590a699e1cb6atree | snapshot
parentdcf101872d03a2394ed5f5aa5b2b036080285e3ccommit | diff
drm/i915/display: Add power well mapping for WCL

WCL has 3 pipes and two TC ports, create power well mapping to reflect
HW. Rest remains similar to Xe3 power well configuration.

v2: Remove TC3/4 ports as they do not exist.

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20250808081931.4101388-1-chaitanya.kumar.borah@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
drivers/gpu/drm/i915/display/intel_display_power_map.c diff | blob | blame | history
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