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(parent: 5599c7c) | patch
clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Mon, 6 Jan 2025 20:28:53 +0000 (20:28 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 3 Feb 2025 10:07:05 +0000 (11:07 +0100)
commit989d673ff7c461b2abd472227fdb7df69860d23f
tree55f2b5b52298184108c02f6b78c2b9d8c540cac6tree | snapshot
parent5599c7c4b4df440aa4a470a5b72669081413981fcommit | diff
clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI

Add clock and reset entries for the DRP-AI block, which is available only
on the Renesas RZ/V2L SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250106202853.262787-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | blame | history
drivers/clk/renesas/rzg2l-cpg.h diff | blob | blame | history
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