]> Gentwo Git Trees - linux/.git/commit
riscv: dts: add clock generator for Sophgo SG2042 SoC
authorChen Wang <unicorn_wang@outlook.com>
Fri, 24 Nov 2023 06:26:02 +0000 (14:26 +0800)
committerChen Wang <unicorn_wang@outlook.com>
Tue, 9 Jul 2024 00:19:52 +0000 (08:19 +0800)
commitb1240a39511b9206293b82ac372c5114d6e15821
treef77a2325aaa3553b48b1da70f20cee3b02d393e4
parent1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
riscv: dts: add clock generator for Sophgo SG2042 SoC

Add clock generator node to device tree for SG2042, and enable clock for
uart.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
arch/riscv/boot/dts/sophgo/sg2042.dtsi