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(parent: fea7a08) | patch
MIPS: Add base architecture support for RI and XI.
authorSteven J. Hill <sjhill@mips.com>
Thu, 13 Sep 2012 21:47:58 +0000 (16:47 -0500)
committerSteven J. Hill <sjhill@mips.com>
Thu, 13 Sep 2012 21:55:53 +0000 (16:55 -0500)
commitb2ab4f08e84d4031f82255447180c559bd076bbf
treec43f3abc03b50d68c73c33750528819e349422e6tree | snapshot
parentfea7a08acb13524b47711625eebea40a0ede69a0commit | diff
MIPS: Add base architecture support for RI and XI.

Originally both Read Inhibit (RI) and Execute Inhibit (XI) were
supported by the TLB only for a SmartMIPS core. The MIPSr3(TM)
Architecture now defines an optional feature to implement these
TLB bits separately. Support for one or both features can be
checked by looking at the Config3.RXI bit.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Acked-by: David Daney <david.daney@cavium.com>
arch/mips/include/asm/cpu-features.h diff | blob | blame | history
arch/mips/include/asm/cpu.h diff | blob | blame | history
arch/mips/include/asm/mipsregs.h diff | blob | blame | history
arch/mips/kernel/cpu-probe.c diff | blob | blame | history
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