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(parent: 969f028) | patch
riscv: traps_misaligned: properly sign extend value in misaligned load handler
authorAndreas Schwab <schwab@suse.de>
Thu, 10 Jul 2025 13:32:18 +0000 (15:32 +0200)
committerPalmer Dabbelt <palmer@dabbelt.com>
Wed, 16 Jul 2025 16:05:39 +0000 (09:05 -0700)
commitb3510183ab7d63c71a3f5c89043d31686a76a34c
tree26513e5da93b95dc56de065eb73d0f4752f88684tree | snapshot
parent969f028bf2c40573ef18061f702ede3ebfe12b42commit | diff
riscv: traps_misaligned: properly sign extend value in misaligned load handler

Add missing cast to signed long.

Signed-off-by: Andreas Schwab <schwab@suse.de>
Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE")
Tested-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/mvmikk0goil.fsf@suse.de
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
arch/riscv/kernel/traps_misaligned.c diff | blob | blame | history
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