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(merge: 836eec3 81fedb3)
Merge branch 'pci/controller/mediatek-gen3'
authorBjorn Helgaas <bhelgaas@google.com>
Fri, 3 Oct 2025 17:13:19 +0000 (12:13 -0500)
committerBjorn Helgaas <bhelgaas@google.com>
Fri, 3 Oct 2025 17:13:19 +0000 (12:13 -0500)
commitdde4b05e26c5077d751ba1ca71aaf2d0bfa8a180
treed570fe2d63b7b51256fee0675824d6130486a29dtree | snapshot
parent836eec3a7c6fe2484bc8701546fe17e11c1b3fffcommit | diff
parent81fedb39a9f0da301a11c7a3b81d91c3b9024462commit | diff
Merge branch 'pci/controller/mediatek-gen3'

- Add optional sys clock ready time setting to avoid sys_clk_rdy signal
  glitching in MT6991 and MT8196 (AngeloGioacchino Del Regno)

- Add DT binding and driver support for MT6991 and MT8196 (AngeloGioacchino
  Del Regno)

* pci/controller/mediatek-gen3:
  PCI: mediatek-gen3: Add support for MediaTek MT8196 SoC
  dt-bindings: PCI: mediatek-gen3: Add support for MT6991/MT8196
  PCI: mediatek-gen3: Implement sys clock ready time setting
Development tree.