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(parent: 0e7107a) | patch
drm/msm/a6xx: Switch to GMU AO counter
authorAkhil P Oommen <akhilpo@oss.qualcomm.com>
Mon, 8 Sep 2025 08:27:02 +0000 (13:57 +0530)
committerRob Clark <robin.clark@oss.qualcomm.com>
Mon, 8 Sep 2025 14:25:00 +0000 (07:25 -0700)
commitf195421318bd00151b3a111af6f315a25c3438a8
tree9ec2827eaccf7215382d064c55b891f23da1d117tree | snapshot
parent0e7107a84d391bfab72d7eb96802920b662812c9commit | diff
drm/msm/a6xx: Switch to GMU AO counter

CP_ALWAYS_ON counter falls under GX domain which is collapsed during
IFPC. So switch to GMU_ALWAYS_ON counter for any CPU reads since it is
not impacted by IFPC. Both counters are clocked by same xo clock source.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673373/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
drivers/gpu/drm/msm/adreno/a6xx_gpu.c diff | blob | blame | history
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