drm/msm/a8xx: Add support for Adreno X2-85 GPU

Adreno X2-85 GPU is found in the next generation of Qualcomm's compute
series chipset called Snapdragon X2 Elite (a.k.a Glymur). It is based
on the new A8x slice architecture and features up to 4 slices. Due to
the wider 12 channel DDR support, there is higher DDR bandwidth available
than previous generation to improve performance.

Add a new entry in the catalog along with the necessary register
configurations to enable support for it.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689026/
Message-ID: <20251118-kaana-gpu-support-v4-18-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index e0bb2c33430145ebb603a3160aed3a8d100fa628..29107b36234641f676f0ec4f930d14a3be537c6d 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1650,6 +1650,108 @@ static const struct adreno_info a7xx_gpus[] = {
 };
 DECLARE_ADRENO_GPULIST(a7xx);
 
+static const struct adreno_reglist_pipe x285_nonctxt_regs[] = {
+       { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
+       { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_RB_GC_GMEM_PROTECT, 0x15000000, BIT(PIPE_BR) },
+       { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
+       { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
+       { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
+       { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
+       { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
+       { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
+       { REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) },
+       { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
+       { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
+       { REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) },
+       { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
+       { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
+       /* Disable CS dead batch merge */
+       { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(31), BIT(PIPE_NONE) },
+       { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
+       { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
+       { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
+       /* BIT(26): Disable final clamp for bicubic filtering */
+       { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) },
+       { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
+       { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
+       { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
+       { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
+       { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
+       { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
+       { },
+};
+
+static const u32 x285_protect_regs[] = {
+       A6XX_PROTECT_RDONLY(0x00008, 0x039b),
+       A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
+       A6XX_PROTECT_NORDWR(0x00440, 0x001f),
+       A6XX_PROTECT_RDONLY(0x00580, 0x005f),
+       A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
+       A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
+       A6XX_PROTECT_RDONLY(0x00759, 0x0026),
+       A6XX_PROTECT_RDONLY(0x00789, 0x0000),
+       A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
+       A6XX_PROTECT_NORDWR(0x00800, 0x0029),
+       A6XX_PROTECT_NORDWR(0x0082c, 0x0000),
+       A6XX_PROTECT_NORDWR(0x00837, 0x00af),
+       A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
+       A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
+       A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
+       A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
+       A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
+       A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
+       A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
+       A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
+       A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
+       A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
+       A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
+       A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
+       A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
+       A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
+       A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
+       A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
+       A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
+       A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
+       A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
+       A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
+       A6XX_PROTECT_NORDWR(0x0ae00, 0x0006),
+       A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
+       A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
+       A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
+       A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
+       A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
+       A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
+       A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
+       A6XX_PROTECT_NORDWR(0x18400, 0x003f),
+       A6XX_PROTECT_RDONLY(0x18440, 0x013f),
+       A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
+       A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
+       A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
+       A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
+       A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
+       A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
+       A6XX_PROTECT_NORDWR(0x27800, 0x007f),
+       A6XX_PROTECT_RDONLY(0x27880, 0x0385),
+       A6XX_PROTECT_NORDWR(0x27882, 0x000a),
+       A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
+};
+
+DECLARE_ADRENO_PROTECT(x285_protect, 64);
+
 static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
        { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
        { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
@@ -1782,6 +1884,36 @@ static const struct adreno_reglist a840_gbif[] = {
 
 static const struct adreno_info a8xx_gpus[] = {
        {
+               .chip_ids = ADRENO_CHIP_IDS(0x44070001),
+               .family = ADRENO_8XX_GEN2,
+               .fw = {
+                       [ADRENO_FW_SQE] = "gen80100_sqe.fw",
+                       [ADRENO_FW_GMU] = "gen80100_gmu.bin",
+               },
+               .gmem = 21 * SZ_1M,
+               .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+                         ADRENO_QUIRK_HAS_HW_APRIV,
+               .funcs = &a8xx_gpu_funcs,
+               .a6xx = &(const struct a6xx_info) {
+                       .protect = &x285_protect,
+                       .nonctxt_reglist = x285_nonctxt_regs,
+                       .gbif_cx = a840_gbif,
+                       .max_slices = 4,
+                       .gmu_chipid = 0x8010100,
+                       .bcms = (const struct a6xx_bcm[]) {
+                               { .name = "SH0", .buswidth = 16 },
+                               { .name = "MC0", .buswidth = 4 },
+                               {
+                                       .name = "ACV",
+                                       .fixed = true,
+                                       .perfmode = BIT(2),
+                                       .perfmode_bw = 16500000,
+                               },
+                               { /* sentinel */ },
+                       },
+               },
+       }, {
                .chip_ids = ADRENO_CHIP_IDS(0x44050a01),
                .family = ADRENO_8XX_GEN2,
                .fw = {

diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
index 43b886ff576dd0545e58badf4aabc71f09cd5ad6..30de078e9dfd2c7d2cec93e810ea6f34723349bb 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
@@ -190,6 +190,9 @@ static void a8xx_set_hwcg(struct msm_gpu *gpu, bool state)
        struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
        u32 val;
 
+       if (adreno_is_x285(adreno_gpu) && state)
+               gpu_write(gpu, REG_A8XX_RBBM_CGC_0_PC, 0x00000702);
+
        gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
                        state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
        gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 7a8cb1ea2a386bd7025b3a5482f76f0ded7a65f4..0f8d3de97636c50a0bc4a32a7d0b3ad106b48523 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -580,6 +580,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gpu)
        return gpu->info->family >= ADRENO_8XX_GEN1;
 }
 
+static inline int adreno_is_x285(struct adreno_gpu *gpu)
+{
+       return gpu->info->chip_ids[0] == 0x44070001;
+}
+
 static inline int adreno_is_a840(struct adreno_gpu *gpu)
 {
        return gpu->info->chip_ids[0] == 0x44050a01;