drm/msm/adreno: Add MMU fault handler to adreno_gpu_func

Move MMU fault handler for each generation to adreno function list. This
will help to use common code for mmu pagefault handler registration between
a6x/a7x and a8x layer.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689007/
Message-ID: <20251118-kaana-gpu-support-v4-8-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 575f2f9d3b1d6efb644a83be5e8012c815a08be1..9edd23d419ec37e5b5672606df2aaa756b60bccd 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2641,7 +2641,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
        adreno_gpu->uche_trap_base = 0x1fffffffff000ull;
 
        msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
-                                 a6xx_fault_handler);
+                                 adreno_gpu->funcs->mmu_fault_handler);
 
        ret = a6xx_calc_ubwc_config(adreno_gpu);
        if (ret) {
@@ -2686,6 +2686,7 @@ const struct adreno_gpu_funcs a6xx_gpu_funcs = {
        .init = a6xx_gpu_init,
        .get_timestamp = a6xx_gmu_get_timestamp,
        .bus_halt = a6xx_bus_clear_pending_transactions,
+       .mmu_fault_handler = a6xx_fault_handler,
 };
 
 const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = {
@@ -2717,6 +2718,7 @@ const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = {
        .init = a6xx_gpu_init,
        .get_timestamp = a6xx_get_timestamp,
        .bus_halt = a6xx_bus_clear_pending_transactions,
+       .mmu_fault_handler = a6xx_fault_handler,
 };
 
 const struct adreno_gpu_funcs a7xx_gpu_funcs = {
@@ -2750,4 +2752,5 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs = {
        .init = a6xx_gpu_init,
        .get_timestamp = a6xx_gmu_get_timestamp,
        .bus_halt = a6xx_bus_clear_pending_transactions,
+       .mmu_fault_handler = a6xx_fault_handler,
 };

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 08bb601b3bd3252c57489f101e0255719b244a74..922d2dee70fbb448c3ede064fdcfb38b1f6f642c 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -78,6 +78,7 @@ struct adreno_gpu_funcs {
        struct msm_gpu *(*init)(struct drm_device *dev);
        int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
        void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off);
+       int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data);
 };
 
 struct adreno_reglist {