]> Gentwo Git Trees - linux/.git/commitdiff
drm/amd/display: Add support for sRGB Inverse EOTF in SHAPER block
authorAlex Hung <alex.hung@amd.com>
Sat, 15 Nov 2025 00:01:54 +0000 (17:01 -0700)
committerSimon Ser <contact@emersion.fr>
Wed, 26 Nov 2025 22:03:34 +0000 (23:03 +0100)
Expose a 2nd curve colorop with support for
DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF and program HW to
perform the sRGB Inverse EOTF on the shaper block
when the colorop is not in bypass.

With this change the follow IGT tests pass:
kms_colorop --run plane-XR30-XR30-srgb_inv_eotf
kms_colorop --run plane-XR30-XR30-srgb_eotf-srgb_inv_eotf

The color pipeline now consists of the following colorops:
1. 1D curve colorop w/ sRGB EOTF support
2. 1D curve colorop w/ sRGB Inverse EOTF support

Signed-off-by: Alex Hung <alex.hung@amd.com>
Co-developed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Simon Ser <contact@emersion.fr>
Link: https://patch.msgid.link/20251115000237.3561250-30-alex.hung@amd.com
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h

index 9751d5b06d0ad01a9eb20959f6f885e01d349b06..ab92a75a7182374f04140537274317d2270ffca8 100644 (file)
@@ -1242,6 +1242,68 @@ __set_dm_plane_colorop_degamma(struct drm_plane_state *plane_state,
        return __set_colorop_in_tf_1d_curve(dc_plane_state, colorop_state);
 }
 
+static int
+__set_colorop_in_shaper_1d_curve(struct dc_plane_state *dc_plane_state,
+                                struct drm_colorop_state *colorop_state)
+{
+       struct dc_transfer_func *tf = &dc_plane_state->in_shaper_func;
+       struct drm_colorop *colorop = colorop_state->colorop;
+       struct drm_device *drm = colorop->dev;
+
+       if (colorop->type != DRM_COLOROP_1D_CURVE &&
+           colorop_state->curve_1d_type != DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF)
+               return -EINVAL;
+
+       if (colorop_state->bypass) {
+               tf->type = TF_TYPE_BYPASS;
+               tf->tf = TRANSFER_FUNCTION_LINEAR;
+               return 0;
+       }
+
+       drm_dbg(drm, "Shaper colorop with ID: %d\n", colorop->base.id);
+
+       if (colorop->type == DRM_COLOROP_1D_CURVE) {
+               tf->type = TF_TYPE_DISTRIBUTED_POINTS;
+               tf->tf = amdgpu_colorop_tf_to_dc_tf(colorop_state->curve_1d_type);
+               tf->sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;
+               return __set_output_tf(tf, 0, 0, false);
+       }
+
+       return -EINVAL;
+}
+
+static int
+__set_dm_plane_colorop_shaper(struct drm_plane_state *plane_state,
+                             struct dc_plane_state *dc_plane_state,
+                             struct drm_colorop *colorop)
+{
+       struct drm_colorop *old_colorop;
+       struct drm_colorop_state *colorop_state = NULL, *new_colorop_state;
+       struct drm_atomic_state *state = plane_state->state;
+       int i = 0;
+
+       old_colorop = colorop;
+
+       /* 2nd op: 1d curve - shaper */
+       for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {
+               if (new_colorop_state->colorop == old_colorop &&
+                   new_colorop_state->curve_1d_type == DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) {
+                       colorop_state = new_colorop_state;
+                       break;
+               }
+
+               if (new_colorop_state->colorop == old_colorop) {
+                       colorop_state = new_colorop_state;
+                       break;
+               }
+       }
+
+       if (!colorop_state)
+               return -EINVAL;
+
+       return __set_colorop_in_shaper_1d_curve(dc_plane_state, colorop_state);
+}
+
 static int
 amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state,
                                     struct dc_plane_state *dc_plane_state)
@@ -1297,6 +1359,7 @@ amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state,
                                       struct dc_plane_state *dc_plane_state)
 {
        struct drm_colorop *colorop = plane_state->color_pipeline;
+       struct drm_device *dev = plane_state->plane->dev;
        int ret;
 
        /* 1D Curve - DEGAM TF */
@@ -1307,6 +1370,17 @@ amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state,
        if (ret)
                return ret;
 
+       /* 1D Curve - SHAPER TF */
+       colorop = colorop->next;
+       if (!colorop) {
+               drm_dbg(dev, "no Shaper TF colorop found\n");
+               return -EINVAL;
+       }
+
+       ret = __set_dm_plane_colorop_shaper(plane_state, dc_plane_state, colorop);
+       if (ret)
+               return ret;
+
        return 0;
 }
 
index d30c189265601a3e0e257c0961ec3f5c96cb02f8..ae8df55f3004315f84f3500c7a760a6254fc4f40 100644 (file)
@@ -34,6 +34,9 @@
 const u64 amdgpu_dm_supported_degam_tfs =
        BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF);
 
+const u64 amdgpu_dm_supported_shaper_tfs =
+       BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF);
+
 #define MAX_COLOR_PIPELINE_OPS 10
 
 int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_prop_enum_list *list)
@@ -59,6 +62,21 @@ int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_pr
        list->type = ops[i]->base.id;
        list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", ops[i]->base.id);
 
+       i++;
+
+       /* 1D curve - SHAPER TF */
+       ops[i] = kzalloc(sizeof(*ops[0]), GFP_KERNEL);
+       if (!ops[i]) {
+               ret = -ENOMEM;
+               goto cleanup;
+       }
+
+       ret = drm_plane_colorop_curve_1d_init(dev, ops[i], plane, amdgpu_dm_supported_shaper_tfs);
+       if (ret)
+               goto cleanup;
+
+       drm_colorop_set_next_property(ops[i - 1], ops[i]);
+
        return 0;
 
 cleanup:
index 3324e2a6607968c893034d13d2b6b1bc10f89f6b..71cd2799452811dd0f3ee043197f2a9743bf68a1 100644 (file)
@@ -28,6 +28,7 @@
 #define __AMDGPU_DM_COLOROP_H__
 
 extern const u64 amdgpu_dm_supported_degam_tfs;
+extern const u64 amdgpu_dm_supported_shaper_tfs;
 
 int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_prop_enum_list *list);