drm/msm/a6xx: Flush LRZ cache before PT switch

As per the recommendation, A7x and newer GPUs should flush the LRZ cache
before switching the pagetable. Update a6xx_set_pagetable() to do this.
While we are at it, sync both BV and BR before issuing  a
CP_RESET_CONTEXT_STATE command, to match the downstream sequence.

Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/688995/
Message-ID: <20251118-kaana-gpu-support-v4-2-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 779c1da7c46dfc604c99f1edbb9565a85d45f653..e6393ef0fd78055463b7cb5b82fe2d49eecaede6 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -224,7 +224,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
                OUT_RING(ring, submit->seqno - 1);
 
                OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
-               OUT_RING(ring, CP_SET_THREAD_BOTH);
+               OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH);
 
                /* Reset state used to synchronize BR and BV */
                OUT_PKT7(ring, CP_RESET_CONTEXT_STATE, 1);
@@ -235,7 +235,13 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
                         CP_RESET_CONTEXT_STATE_0_RESET_GLOBAL_LOCAL_TS);
 
                OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
-               OUT_RING(ring, CP_SET_THREAD_BR);
+               OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH);
+
+               OUT_PKT7(ring, CP_EVENT_WRITE, 1);
+               OUT_RING(ring, LRZ_FLUSH);
+
+               OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
+               OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR);
        }
 
        if (!sysprof) {