arm64: dts: visconti: Update the clock providers for SPI

Remove fixed clock and source common clock for SPI.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Link: https://lore.kernel.org/r/20220510015229.139818-5-nobuhiro1.iwamatsu@toshiba.co.jp/

diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi
index adfe8406c24ce899f97cf014bed5b43bacd6772f..0c8321022a73abeb085d2c8916253aa888fdbbdf 100644 (file)
--- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi
+++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi
@@ -25,8 +25,6 @@ &spi0_pins {
 
 &spi0 {
        status = "okay";
-       clocks = <&clk300mhz>, <&clk150mhz>;
-       clock-names = "sspclk", "apb_pclk";
 
        mmc-slot@0 {
                compatible = "mmc-spi-slot";

diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
index 6050796a1678c2d43e453ac0d45a0516ea95becb..196cda7b5d9028aff4a021398296d1273537ffdb 100644 (file)
--- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
+++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
@@ -143,13 +143,6 @@ clk125mhz: clk125mhz {
                clock-output-names = "clk125mhz";
        };
 
-       clk150mhz: clk150mhz {
-               compatible = "fixed-clock";
-               clock-frequency = <150000000>;
-               #clock-cells = <0>;
-               clock-output-names = "clk150mhz";
-       };
-
        clk300mhz: clk300mhz {
                compatible = "fixed-clock";
                clock-frequency = <300000000>;
@@ -395,6 +388,8 @@ spi0: spi@28140000 {
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       clocks = <&pismu TMPV770X_CLK_PISPI1>;
+                       clock-names = "apb_pclk";
                        status = "disabled";
                };
 
@@ -407,6 +402,8 @@ spi1: spi@28141000 {
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       clocks = <&pismu TMPV770X_CLK_PISPI1>;
+                       clock-names = "apb_pclk";
                        status = "disabled";
                };
 
@@ -419,6 +416,8 @@ spi2: spi@28142000 {
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       clocks = <&pismu TMPV770X_CLK_PISPI2>;
+                       clock-names = "apb_pclk";
                        status = "disabled";
                };
 
@@ -431,6 +430,8 @@ spi3: spi@28143000 {
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       clocks = <&pismu TMPV770X_CLK_PISPI3>;
+                       clock-names = "apb_pclk";
                        status = "disabled";
                };
 
@@ -443,6 +444,8 @@ spi4: spi@28144000 {
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       clocks = <&pismu TMPV770X_CLK_PISPI4>;
+                       clock-names = "apb_pclk";
                        status = "disabled";
                };
 
@@ -455,6 +458,8 @@ spi5: spi@28145000 {
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       clocks = <&pismu TMPV770X_CLK_PISPI5>;
+                       clock-names = "apb_pclk";
                        status = "disabled";
                };
 
@@ -467,6 +472,8 @@ spi6: spi@28146000 {
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       clocks = <&pismu TMPV770X_CLK_PISPI6>;
+                       clock-names = "apb_pclk";
                        status = "disabled";
                };