i3c: master: svc: Prevent incomplete IBI transaction

If no free IBI slot is available, svc_i3c_master_handle_ibi returns
immediately. This causes the STOP condition to be missed because the
EmitStop request is sent when the transfer is not complete. To resolve
this, svc_i3c_master_handle_ibi must wait for the transfer to complete
before returning.

Fixes: dd3c52846d59 ("i3c: master: svc: Add Silvaco I3C master driver")
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20251027034715.708243-1-yschu@nuvoton.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
index 9641e66a4e5f2da3bd84b30fa741e5e19d87465d..e70a64f2a32fa547f90bd8d6957b7d1857f6871e 100644 (file)
--- a/drivers/i3c/master/svc-i3c-master.c
+++ b/drivers/i3c/master/svc-i3c-master.c
@@ -406,21 +406,27 @@ static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master,
        int ret, val;
        u8 *buf;
 
-       slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
-       if (!slot)
-               return -ENOSPC;
-
-       slot->len = 0;
-       buf = slot->data;
-
+       /*
+        * Wait for transfer to complete before returning. Otherwise, the EmitStop
+        * request might be sent when the transfer is not complete.
+        */
        ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
                                                SVC_I3C_MSTATUS_COMPLETE(val), 0, 1000);
        if (ret) {
                dev_err(master->dev, "Timeout when polling for COMPLETE\n");
-               i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
                return ret;
        }
 
+       slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
+       if (!slot) {
+               dev_dbg(master->dev, "No free ibi slot, drop the data\n");
+               writel(SVC_I3C_MDATACTRL_FLUSHRB, master->regs + SVC_I3C_MDATACTRL);
+               return -ENOSPC;
+       }
+
+       slot->len = 0;
+       buf = slot->data;
+
        while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS))  &&
               slot->len < SVC_I3C_FIFO_SIZE) {
                mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL);