pmdomain: mediatek: Add support for MT8196 HFRPSYS power domains

Add support for the HFRPSYS Multimedia power domains found in the
MediaTek MT8196 Chromebook SoC.
Those power domains are all managed by the Hardware Voter MCU.

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/pmdomain/mediatek/mt8196-pm-domains.h b/drivers/pmdomain/mediatek/mt8196-pm-domains.h
index ce8d594c46f84e84cdd23b541cf430881b288587..2e4b287206596ca04d09348462729227051b1604 100644 (file)
--- a/drivers/pmdomain/mediatek/mt8196-pm-domains.h
+++ b/drivers/pmdomain/mediatek/mt8196-pm-domains.h
@@ -369,6 +369,239 @@ static const struct scpsys_hwv_domain_data scpsys_hwv_domain_data_mt8196[] = {
        },
 };
 
+static const struct scpsys_hwv_domain_data hfrpsys_hwv_domain_data_mt8196[] = {
+       [MT8196_POWER_DOMAIN_VDE0] = {
+               .name = "vde0",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 7,
+       },
+       [MT8196_POWER_DOMAIN_VDE1] = {
+               .name = "vde1",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 8,
+       },
+       [MT8196_POWER_DOMAIN_VDE_VCORE0] = {
+               .name = "vde-vcore0",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 9,
+       },
+       [MT8196_POWER_DOMAIN_VEN0] = {
+               .name = "ven0",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 10,
+       },
+       [MT8196_POWER_DOMAIN_VEN1] = {
+               .name = "ven1",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 11,
+       },
+       [MT8196_POWER_DOMAIN_VEN2] = {
+               .name = "ven2",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 12,
+       },
+       [MT8196_POWER_DOMAIN_DISP_VCORE] = {
+               .name = "disp-vcore",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 24,
+       },
+       [MT8196_POWER_DOMAIN_DIS0_DORMANT] = {
+               .name = "dis0-dormant",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 25,
+       },
+       [MT8196_POWER_DOMAIN_DIS1_DORMANT] = {
+               .name = "dis1-dormant",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 26,
+       },
+       [MT8196_POWER_DOMAIN_OVL0_DORMANT] = {
+               .name = "ovl0-dormant",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 27,
+       },
+       [MT8196_POWER_DOMAIN_OVL1_DORMANT] = {
+               .name = "ovl1-dormant",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 28,
+       },
+       [MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT] = {
+               .name = "disp-edptx-dormant",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 29,
+       },
+       [MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT] = {
+               .name = "disp-dptx-dormant",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 30,
+       },
+       [MT8196_POWER_DOMAIN_MML0_SHUTDOWN] = {
+               .name = "mml0-shutdown",
+               .set = 0x0218,
+               .clr = 0x021C,
+               .done = 0x141C,
+               .en = 0x1410,
+               .set_sta = 0x146C,
+               .clr_sta = 0x1470,
+               .setclr_bit = 31,
+       },
+       [MT8196_POWER_DOMAIN_MML1_SHUTDOWN] = {
+               .name = "mml1-shutdown",
+               .set = 0x0220,
+               .clr = 0x0224,
+               .done = 0x142C,
+               .en = 0x1420,
+               .set_sta = 0x1474,
+               .clr_sta = 0x1478,
+               .setclr_bit = 0,
+       },
+       [MT8196_POWER_DOMAIN_MM_INFRA0] = {
+               .name = "mm-infra0",
+               .set = 0x0220,
+               .clr = 0x0224,
+               .done = 0x142C,
+               .en = 0x1420,
+               .set_sta = 0x1474,
+               .clr_sta = 0x1478,
+               .setclr_bit = 1,
+       },
+       [MT8196_POWER_DOMAIN_MM_INFRA1] = {
+               .name = "mm-infra1",
+               .set = 0x0220,
+               .clr = 0x0224,
+               .done = 0x142C,
+               .en = 0x1420,
+               .set_sta = 0x1474,
+               .clr_sta = 0x1478,
+               .setclr_bit = 2,
+       },
+       [MT8196_POWER_DOMAIN_MM_INFRA_AO] = {
+               .name = "mm-infra-ao",
+               .set = 0x0220,
+               .clr = 0x0224,
+               .done = 0x142C,
+               .en = 0x1420,
+               .set_sta = 0x1474,
+               .clr_sta = 0x1478,
+               .setclr_bit = 3,
+       },
+       [MT8196_POWER_DOMAIN_CSI_BS_RX] = {
+               .name = "csi-bs-rx",
+               .set = 0x0220,
+               .clr = 0x0224,
+               .done = 0x142C,
+               .en = 0x1420,
+               .set_sta = 0x1474,
+               .clr_sta = 0x1478,
+               .setclr_bit = 5,
+       },
+       [MT8196_POWER_DOMAIN_CSI_LS_RX] = {
+               .name = "csi-ls-rx",
+               .set = 0x0220,
+               .clr = 0x0224,
+               .done = 0x142C,
+               .en = 0x1420,
+               .set_sta = 0x1474,
+               .clr_sta = 0x1478,
+               .setclr_bit = 6,
+       },
+       [MT8196_POWER_DOMAIN_DSI_PHY0] = {
+               .name = "dsi-phy0",
+               .set = 0x0220,
+               .clr = 0x0224,
+               .done = 0x142C,
+               .en = 0x1420,
+               .set_sta = 0x1474,
+               .clr_sta = 0x1478,
+               .setclr_bit = 7,
+       },
+       [MT8196_POWER_DOMAIN_DSI_PHY1] = {
+               .name = "dsi-phy1",
+               .set = 0x0220,
+               .clr = 0x0224,
+               .done = 0x142C,
+               .en = 0x1420,
+               .set_sta = 0x1474,
+               .clr_sta = 0x1478,
+               .setclr_bit = 8,
+       },
+       [MT8196_POWER_DOMAIN_DSI_PHY2] = {
+               .name = "dsi-phy2",
+               .set = 0x0220,
+               .clr = 0x0224,
+               .done = 0x142C,
+               .en = 0x1420,
+               .set_sta = 0x1474,
+               .clr_sta = 0x1478,
+               .setclr_bit = 9,
+       },
+};
+
 static const struct scpsys_soc_data mt8196_scpsys_data = {
        .domains_data = scpsys_domain_data_mt8196,
        .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8196),
@@ -383,4 +616,10 @@ static const struct scpsys_soc_data mt8196_scpsys_hwv_data = {
        .type = SCPSYS_MTCMOS_TYPE_HW_VOTER,
 };
 
+static const struct scpsys_soc_data mt8196_hfrpsys_hwv_data = {
+       .hwv_domains_data = hfrpsys_hwv_domain_data_mt8196,
+       .num_hwv_domains = ARRAY_SIZE(hfrpsys_hwv_domain_data_mt8196),
+       .type = SCPSYS_MTCMOS_TYPE_HW_VOTER,
+};
+
 #endif /* __SOC_MEDIATEK_MT8196_PM_DOMAINS_H */

diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c
index 18f0b9b960d9764d18b8c5b187e80c5bd6252198..ac144ab8fce0f1b80f355ade5adda679367da7a5 100644 (file)
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.c
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c
@@ -1158,6 +1158,10 @@ static const struct of_device_id scpsys_of_match[] = {
                .compatible = "mediatek,mt8196-power-controller",
                .data = &mt8196_scpsys_data,
        },
+       {
+               .compatible = "mediatek,mt8196-hwv-hfrp-power-controller",
+               .data = &mt8196_hfrpsys_hwv_data,
+       },
        {
                .compatible = "mediatek,mt8196-hwv-scp-power-controller",
                .data = &mt8196_scpsys_hwv_data,