u32 hs_settle;
u32 clk_settle;
+ unsigned int num_data_lanes;
+
spinlock_t slock; /* Protect events */
struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
struct dentry *debugfs_root;
val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL);
val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE;
if (on) {
- mask = (1 << (csis->bus.num_data_lanes + 1)) - 1;
+ mask = (1 << (csis->num_data_lanes + 1)) - 1;
val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE);
}
mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val);
/* Calculate the line rate from the pixel rate. */
link_freq = v4l2_get_link_freq(csis->source.pad, csis_fmt->width,
- csis->bus.num_data_lanes * 2);
+ csis->num_data_lanes * 2);
if (link_freq < 0) {
dev_err(csis->dev, "Unable to obtain link frequency: %d\n",
(int)link_freq);
const struct v4l2_mbus_framefmt *format,
const struct csis_pix_format *csis_fmt)
{
- int lanes = csis->bus.num_data_lanes;
+ int lanes = csis->num_data_lanes;
u32 val;
val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
}
csis->bus = vep.bus.mipi_csi2;
+ csis->num_data_lanes = csis->bus.num_data_lanes;
- dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes);
+ dev_dbg(csis->dev, "max data lanes: %d\n", csis->bus.num_data_lanes);
dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags);
asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep,