drm/rockchip: dw_hdmi_qp: Use bit macros for RK3576 regs

For consistency and improved readability, redefine a few RK3576 specific
register configurations by relying on GENMASK() and unshifted values for
color depth and output format.  Those are not used at the moment, but
will be needed soon to support the related features.

While at it, drop a few other defines which are unlikely to be ever
required.

Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20251021-rk3588-10bpc-v3-4-3d3eed00a6db@collabora.com

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
index 69c001f4e9057e07469701e13fa92116ef043858..2480f5efd3282db2d1eb581bf9e8083161023705 100644 (file)
--- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
@@ -39,21 +39,16 @@
 #define RK3576_HDMI_HDCP14_MEM_EN      BIT(15)
 
 #define RK3576_VO0_GRF_SOC_CON8                0x0020
-#define RK3576_COLOR_FORMAT_MASK       (0xf << 4)
-#define RK3576_COLOR_DEPTH_MASK                (0xf << 8)
-#define RK3576_RGB                     (0 << 4)
-#define RK3576_YUV422                  (0x1 << 4)
-#define RK3576_YUV444                  (0x2 << 4)
-#define RK3576_YUV420                  (0x3 << 4)
-#define RK3576_8BPC                    (0x0 << 8)
-#define RK3576_10BPC                   (0x6 << 8)
+#define RK3576_COLOR_DEPTH_MASK                GENMASK(11, 8)
+#define RK3576_8BPC                    0x0
+#define RK3576_10BPC                   0x6
+#define RK3576_COLOR_FORMAT_MASK       GENMASK(7, 4)
+#define RK3576_RGB                     0x9
+#define RK3576_YUV422                  0x1
+#define RK3576_YUV444                  0x2
+#define RK3576_YUV420                  0x3
 #define RK3576_CECIN_MASK              BIT(3)
 
-#define RK3576_VO0_GRF_SOC_CON12       0x0030
-#define RK3576_GRF_OSDA_DLYN           (0xf << 12)
-#define RK3576_GRF_OSDA_DIV            (0x7f << 1)
-#define RK3576_GRF_OSDA_DLY_EN         BIT(0)
-
 #define RK3576_VO0_GRF_SOC_CON14       0x0038
 #define RK3576_I2S_SEL_MASK            BIT(0)
 #define RK3576_SPDIF_SEL_MASK          BIT(1)