irqchip/sifive-plic: Fix call to __plic_toggle() in M-Mode code path

The code path for M-Mode linux that disables interrupts for other contexts
was missed when refactoring __plic_toggle().

Since the new version caches updates to the state for the primary context,
its use in this codepath is no longer desireable even if it could be made
correct.

Replace the calls to __plic_toggle() with a loop that simply disables all
of the interrupts in groups of 32 with a direct mmio write.

Fixes: 14ff9e54dd14 ("irqchip/sifive-plic: Cache the interrupt enable state")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Charles Mirabile <cmirabil@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://patch.msgid.link/20251103161813.2437427-1-cmirabil@redhat.com
Closes: https://lore.kernel.org/oe-kbuild-all/202510271316.AQM7gCCy-lkp@intel.com/

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index c03340e7117cd9ca6fe03e21bfee98f1c393c4c5..c5db7d6e3f7cad9dc815e84ad6bc94683845d858 100644 (file)
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -679,12 +679,11 @@ static int plic_probe(struct fwnode_handle *fwnode)
                if (parent_hwirq != RV_IRQ_EXT) {
                        /* Disable S-mode enable bits if running in M-mode. */
                        if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
-                               void __iomem *enable_base = priv->regs +
-                                       CONTEXT_ENABLE_BASE +
-                                       i * CONTEXT_ENABLE_SIZE;
+                               u32 __iomem *enable_base = priv->regs + CONTEXT_ENABLE_BASE +
+                                                          i * CONTEXT_ENABLE_SIZE;
 
-                               for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
-                                       __plic_toggle(enable_base, hwirq, 0);
+                               for (int j = 0; j <= nr_irqs / 32; j++)
+                                       writel(0, enable_base + j);
                        }
                        continue;
                }