arm64: dts: imx8mq-librem5-devkit: Align pin configuration group names with schema

Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:

    ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
index a80e53428c2f86535b571554f71645fbe351c6da..10f30ff85fd3948c91387e730db431c82f70a6f0 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
@@ -735,7 +735,7 @@ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B             0xc1
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x8d
                        MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xcd
@@ -752,7 +752,7 @@ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B             0xc1
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x9f
                        MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xdf
@@ -769,13 +769,13 @@ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B           0xc1
                >;
        };
 
-       pinctrl_usdhc2_pwr: usdhc2grppwr {
+       pinctrl_usdhc2_pwr: usdhc2pwrgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
                >;
        };
 
-       pinctrl_usdhc2_gpio: usdhc2grpgpio {
+       pinctrl_usdhc2_gpio: usdhc2gpiogrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20          0x80 /* WIFI_WAKE */
                >;
@@ -792,7 +792,7 @@ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
                >;
        };
 
-       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK         0x8d
                        MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD         0xcd
@@ -803,7 +803,7 @@ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
                >;
        };
 
-       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK         0x9f
                        MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD         0xcf