drm/msm/dpu: Use dedicated WB number definition

Currently MAX_CHANNELS_PER_ENC is defined as 2, because 2 channels are
supported at most in one encoder. The case of 4 channels per encoder is
to be added. To avoid breaking current WB usage case, use dedicated WB
definition before 4 WB usage case is supported in future.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/675410/
Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-6-ff6232e3472f@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d0ed9e3a33892132f982dbe33a2a524a213510cf..9f3957f24c6a3dc110a4d0b31bb65fe290be4ee4 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -56,6 +56,7 @@
        (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
 
 #define MAX_CHANNELS_PER_ENC 2
+#define MAX_CWB_PER_ENC 2
 
 #define IDLE_SHORT_TIMEOUT     1
 
@@ -182,7 +183,7 @@ struct dpu_encoder_virt {
        struct dpu_encoder_phys *cur_master;
        struct dpu_encoder_phys *cur_slave;
        struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
-       struct dpu_hw_cwb *hw_cwb[MAX_CHANNELS_PER_ENC];
+       struct dpu_hw_cwb *hw_cwb[MAX_CWB_PER_ENC];
        struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
 
        unsigned int dsc_mask;
@@ -2386,7 +2387,7 @@ void dpu_encoder_helper_phys_setup_cwb(struct dpu_encoder_phys *phys_enc,
         */
        cwb_cfg.input = INPUT_MODE_LM_OUT;
 
-       for (int i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
+       for (int i = 0; i < MAX_CWB_PER_ENC; i++) {
                hw_cwb = dpu_enc->hw_cwb[i];
                if (!hw_cwb)
                        continue;