PCI: dwc: Fix wrong PORT_LOGIC_LTSSM_STATE_MASK definition

As per DesignWare Cores PCI Express Controller Databook, section 5.50,
SII: Debug Signals, cxpl_debug_info[63:0]:

  [5:0] smlh_ltssm_state: LTSSM current state. Encoding is same as the
  dedicated smlh_ltssm_state output.

The mask should be 6 bits, from 0 to 5. Hence, fix the mask definition.

Fixes: 23fe5bd4be90 ("PCI: keystone: Cleanup ks_pcie_link_up()")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
[mani: reworded description]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/1763122140-203068-1-git-send-email-shawn.lin@rock-chips.com

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index e995f692a1ecd10130d3be3358827f801811387f..24bfa5231923a15579e109219aedc3a4ca0b2fc6 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -97,7 +97,7 @@
 #define PORT_LANE_SKEW_INSERT_MASK     GENMASK(23, 0)
 
 #define PCIE_PORT_DEBUG0               0x728
-#define PORT_LOGIC_LTSSM_STATE_MASK    0x1f
+#define PORT_LOGIC_LTSSM_STATE_MASK    0x3f
 #define PORT_LOGIC_LTSSM_STATE_L0      0x11
 #define PCIE_PORT_DEBUG1               0x72C
 #define PCIE_PORT_DEBUG1_LINK_UP               BIT(4)