Merge tag 'v6.18-rc6' into drm-next

Linux 6.18-rc6

Backmerge in order to merge msm next

Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --cc .mailmap
Simple merge

diff --cc MAINTAINERS
Simple merge

diff --cc drivers/dma-buf/dma-fence.c
Simple merge

diff --cc drivers/gpu/drm/Makefile
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index c1461317eb29877446e69562a58e17a77203a79e,ed3bef1edfe44ee4de6c08991559f204623090a4..e22cfa7c6d32f286de94c6e0947c20db41894b68
--- 1/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
--- 2/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@@ -81,17 -81,16 +81,29 @@@ static int amdgpu_dma_buf_attach(struc
        struct drm_gem_object *obj = dmabuf->priv;
        struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
        struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 +      int r;
 +
 +      /*
 +       * Disable peer-to-peer access for DCC-enabled VRAM surfaces on GFX12+.
 +       * Such buffers cannot be safely accessed over P2P due to device-local
 +       * compression metadata. Fallback to system-memory path instead.
 +       * Device supports GFX12 (GC 12.x or newer)
 +       * BO was created with the AMDGPU_GEM_CREATE_GFX12_DCC flag
 +       *
 +       */
 +      if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0) &&
++          bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
++              attach->peer2peer = false;
+ 
+       /*
+        * Disable peer-to-peer access for DCC-enabled VRAM surfaces on GFX12+.
+        * Such buffers cannot be safely accessed over P2P due to device-local
+        * compression metadata. Fallback to system-memory path instead.
+        * Device supports GFX12 (GC 12.x or newer)
+        * BO was created with the AMDGPU_GEM_CREATE_GFX12_DCC flag
+        *
+        */
+       if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0) &&
            bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
                attach->peer2peer = false;
  

diff --cc drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index 5e2813e9ae2feb47ca129165a15827bed48b6b1b,62a39204fe0b7df3c93f2ae355c102181cb2b9ef..c21eb34b8cc3de1f0531bb3d84f3159449f66d6f
--- 1/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
--- 2/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@@ -51,31 -51,7 +51,30 @@@
  
  #define MAX_LINKS (MAX_DPIA + MAX_CONNECTOR + MAX_VIRTUAL_LINKS)
  
 +/**
 + * define MAX_DIG_LINK_ENCODERS - maximum number of digital encoders
 + *
 + * Digital encoders are ENGINE_ID_DIGA...G, there are at most 7,
 + * although not every GPU may have that many.
 + */
  #define MAX_DIG_LINK_ENCODERS 7
- #define MAX_DIG_LINK_ENCODERS 7
 +
 +/**
 + * define MAX_DAC_LINK_ENCODERS - maximum number of analog link encoders
 + *
 + * Analog encoders are ENGINE_ID_DACA/B, there are at most 2,
 + * although not every GPU may have that many. Modern GPUs typically
 + * don't have analog encoders.
 + */
 +#define MAX_DAC_LINK_ENCODERS 2
 +
 +/**
 + * define MAX_LINK_ENCODERS - maximum number link encoders in total
 + *
 + * This includes both analog and digital encoders.
 + */
 +#define MAX_LINK_ENCODERS (MAX_DIG_LINK_ENCODERS + MAX_DAC_LINK_ENCODERS)
 +
  #define MAX_DWB_PIPES 1
  #define MAX_HPO_DP2_ENCODERS  4
  #define MAX_HPO_DP2_LINK_ENCODERS     4

diff --cc drivers/gpu/drm/ast/ast_drv.h
Simple merge

diff --cc drivers/gpu/drm/drm_gem_atomic_helper.c
Simple merge

diff --cc drivers/gpu/drm/etnaviv/etnaviv_buffer.c
Simple merge

diff --cc drivers/gpu/drm/i915/Makefile
Simple merge

diff --cc drivers/gpu/drm/imx/ipuv3/parallel-display.c
Simple merge

diff --cc drivers/gpu/drm/mediatek/mtk_crtc.c
Simple merge

diff --cc drivers/gpu/drm/mediatek/mtk_plane.c
Simple merge

diff --cc drivers/gpu/drm/msm/msm_gem.c
Simple merge

diff --cc drivers/gpu/drm/panthor/panthor_gem.c
Simple merge

diff --cc drivers/gpu/drm/panthor/panthor_mmu.c
Simple merge

diff --cc drivers/gpu/drm/xe/xe_exec_queue.c
index 8724f8de67e2738dffef72aeab2a67d8cfe35656,cb5f204c08ed6e9b73fe9f1baecd784fbecdbfb3..12adfc3a05473ec3765bbae25470822b676ae6a0
--- 1/drivers/gpu/drm/xe/xe_exec_queue.c
--- 2/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@@ -387,10 -343,7 +387,13 @@@ void xe_exec_queue_destroy(struct kref 
  {
        struct xe_exec_queue *q = container_of(ref, struct xe_exec_queue, refcount);
        struct xe_exec_queue *eq, *next;
 +      int i;
 +
 +      xe_assert(gt_to_xe(q->gt), atomic_read(&q->job_cnt) == 0);
 +
++      if (q->ufence_syncobj)
++              drm_syncobj_put(q->ufence_syncobj);
+ 
        if (q->ufence_syncobj)
                drm_syncobj_put(q->ufence_syncobj);
  

diff --cc drivers/gpu/drm/xe/xe_gt.c
index 6d479948bf21f470b50f894b2fa913fc8fe8a095,6d3db5e55d98ae3dcf9fb4a3a766edd34ab2302e..dbb5e7a9bc6a962e1e2938f05d4fde4f51a62b0c
--- 1/drivers/gpu/drm/xe/xe_gt.c
--- 2/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@@ -875,13 -872,21 +875,12 @@@ static void gt_reset_worker(struct work
  err_out:
        xe_force_wake_put(gt_to_fw(gt), fw_ref);
        XE_WARN_ON(xe_uc_start(&gt->uc));
 +
  err_fail:
        xe_gt_err(gt, "reset failed (%pe)\n", ERR_PTR(err));
 -
        xe_device_declare_wedged(gt_to_xe(gt));
- 
  err_pm_put:
        xe_pm_runtime_put(gt_to_xe(gt));
 -
 -      return err;
 -}
 -
 -static void gt_reset_worker(struct work_struct *w)
 -{
 -      struct xe_gt *gt = container_of(w, typeof(*gt), reset.worker);
 -
 -      gt_reset(gt);
  }
  
  void xe_gt_reset_async(struct xe_gt *gt)

diff --cc drivers/video/fbdev/core/bitblit.c
Simple merge

diff --cc drivers/video/fbdev/core/fbcon.c
Simple merge