drm/i915/color: Create a transfer function color pipeline

Add a color pipeline with three colorops in the sequence

        1D LUT - 3x4 CTM - 1D LUT

This pipeline can be used to do any color space conversion or HDR
tone mapping

v2: Change namespace to drm_plane_colorop*
v3: Use simpler/pre-existing colorops for first iteration
v4:
 - s/*_tf_*/*_color_* (Jani)
 - Refactor to separate files (Jani)
 - Add missing space in comment (Suraj)
 - Consolidate patch that adds/attaches pipeline property
v5:
 - Limit MAX_COLOR_PIPELINES to 2.(Suraj)
	Increase it as and when we add more pipelines.
 - Remove redundant initialization code (Suraj)
v6:
 - Use drm_plane_create_color_pipeline_property() (Arun)
	Now MAX_COLOR_PIPELINES is 1

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://patch.msgid.link/20251203085211.3663374-5-uma.shankar@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f1ca1413a0dc7c2b46206f9acceed427b751aa2d..4db24050edb0e2e8346ebd2b08e17ee48af76261 100644 (file)
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -240,6 +240,7 @@ i915-y += \
        display/intel_cmtg.o \
        display/intel_color.o \
        display/intel_colorop.o \
+       display/intel_color_pipeline.o \
        display/intel_combo_phy.o \
        display/intel_connector.o \
        display/intel_crtc.o \

diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
new file mode 100644 (file)
index 0000000..489d470
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+#include "intel_colorop.h"
+#include "intel_color_pipeline.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "skl_universal_plane.h"
+
+#define MAX_COLOR_PIPELINES 1
+#define PLANE_DEGAMMA_SIZE 128
+#define PLANE_GAMMA_SIZE 32
+
+static
+int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list)
+{
+       struct intel_colorop *colorop;
+       struct drm_device *dev = plane->dev;
+       int ret;
+       struct drm_colorop *prev_op;
+
+       colorop = intel_colorop_create(INTEL_PLANE_CB_PRE_CSC_LUT);
+
+       ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
+                                                 PLANE_DEGAMMA_SIZE,
+                                                 DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
+                                                 DRM_COLOROP_FLAG_ALLOW_BYPASS);
+
+       if (ret)
+               return ret;
+
+       list->type = colorop->base.base.id;
+       list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", colorop->base.base.id);
+
+       /* TODO: handle failures and clean up */
+       prev_op = &colorop->base;
+
+       colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
+       ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
+                                            DRM_COLOROP_FLAG_ALLOW_BYPASS);
+       if (ret)
+               return ret;
+
+       drm_colorop_set_next_property(prev_op, &colorop->base);
+       prev_op = &colorop->base;
+
+       colorop = intel_colorop_create(INTEL_PLANE_CB_POST_CSC_LUT);
+       ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
+                                                 PLANE_GAMMA_SIZE,
+                                                 DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
+                                                 DRM_COLOROP_FLAG_ALLOW_BYPASS);
+       if (ret)
+               return ret;
+
+       drm_colorop_set_next_property(prev_op, &colorop->base);
+
+       return 0;
+}
+
+int intel_color_pipeline_plane_init(struct drm_plane *plane)
+{
+       struct drm_device *dev = plane->dev;
+       struct intel_display *display = to_intel_display(dev);
+       struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES];
+       int len = 0;
+       int ret;
+
+       /* Currently expose pipeline only for HDR planes */
+       if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
+               return 0;
+
+       /* Add pipeline consisting of transfer functions */
+       ret = _intel_color_pipeline_plane_init(plane, &pipelines[len]);
+       if (ret)
+               return ret;
+       len++;
+
+       return drm_plane_create_color_pipeline_property(plane, pipelines, len);
+}

diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.h b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
new file mode 100644 (file)
index 0000000..7f1d32b
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_COLOR_PIPELINE_H__
+#define __INTEL_COLOR_PIPELINE_H__
+
+struct drm_plane;
+
+int intel_color_pipeline_plane_init(struct drm_plane *plane);
+
+#endif /* __INTEL_COLOR_PIPELINE_H__ */

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index e468407c9457c67914de21687b2e0310b13432fc..aa666f4c032463ab1eb36d3644ec35d7f171072f 100644 (file)
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -243,6 +243,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
        i915-display/intel_cmtg.o \
        i915-display/intel_color.o \
        i915-display/intel_colorop.o \
+       i915-display/intel_color_pipeline.o \
        i915-display/intel_combo_phy.o \
        i915-display/intel_connector.o \
        i915-display/intel_crtc.o \