From 1ef05ef9fa02188d859b2ee6a45e1a4c38420639 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Tue, 18 Nov 2025 14:20:36 +0530 Subject: [PATCH] drm/msm/a6xx: Sync latest register definitions Sync the latest register definitions from Mesa which includes the updates for A8x family. Co-developed-by: Rob Clark Signed-off-by: Rob Clark Signed-off-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/689009/ Message-ID: <20251118-kaana-gpu-support-v4-9-86eeb8e93fb6@oss.qualcomm.com> --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 +- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 8 +- .../drm/msm/adreno/adreno_gen7_0_0_snapshot.h | 8 +- .../drm/msm/adreno/adreno_gen7_2_0_snapshot.h | 8 +- .../drm/msm/adreno/adreno_gen7_9_0_snapshot.h | 8 +- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 2197 ++++++++++++----- .../drm/msm/registers/adreno/a6xx_enums.xml | 2 +- .../msm/registers/adreno/a8xx_descriptors.xml | 121 + .../drm/msm/registers/adreno/a8xx_enums.xml | 299 +++ .../msm/registers/adreno/adreno_common.xml | 1 + .../drm/msm/registers/adreno/adreno_pm4.xml | 361 ++- 12 files changed, 2339 insertions(+), 691 deletions(-) create mode 100644 drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml create mode 100644 drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 0c0dfb25f01b..7acf2cc13cd0 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -201,6 +201,7 @@ ADRENO_HEADERS = \ generated/a6xx_perfcntrs.xml.h \ generated/a7xx_enums.xml.h \ generated/a7xx_perfcntrs.xml.h \ + generated/a8xx_enums.xml.h \ generated/a6xx_gmu.xml.h \ generated/adreno_common.xml.h \ generated/adreno_pm4.xml.h \ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 9edd23d419ec..2f06e7e7d87f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -238,7 +238,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH); OUT_PKT7(ring, CP_EVENT_WRITE, 1); - OUT_RING(ring, LRZ_FLUSH); + OUT_RING(ring, LRZ_FLUSH_INVALIDATE); OUT_PKT7(ring, CP_THREAD_CONTROL, 1); OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); @@ -381,7 +381,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) rbmemptr_stats(ring, index, alwayson_end)); /* Write the fence to the scratch register */ - OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); + OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1); OUT_RING(ring, submit->seqno); /* @@ -522,7 +522,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) rbmemptr_stats(ring, index, alwayson_end)); /* Write the fence to the scratch register */ - OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); + OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1); OUT_RING(ring, submit->seqno); OUT_PKT7(ring, CP_THREAD_CONTROL, 1); @@ -1305,7 +1305,7 @@ static int hw_init(struct msm_gpu *gpu) } if (adreno_is_a660_family(adreno_gpu)) - gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); + gpu_write(gpu, REG_A7XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); /* Setting the mem pool size */ if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) { @@ -1754,10 +1754,10 @@ static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *da const char *block = "unknown"; u32 scratch[] = { - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH(4)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH(5)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH(6)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH(7)), }; if (info) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h index 4c5fe627d368..688b8ce02fdc 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h @@ -71,8 +71,8 @@ static const struct a6xx_cluster { u32 sel_val; } a6xx_clusters[] = { CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0), - CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0), - CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9), + CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0), + CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9), CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0), CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0), CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0), @@ -303,8 +303,8 @@ static const u32 a660_registers[] = { static const struct a6xx_registers a6xx_reglist[] = { REGS(a6xx_registers, 0, 0), REGS(a660_registers, 0, 0), - REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0), - REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9), + REGS(a6xx_rb_rac_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0), + REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 9), }; static const u32 a6xx_ahb_registers[] = { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h index 087473679893..d513e03fef08 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h @@ -691,14 +691,14 @@ static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_registers[] = { static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_lpac_registers), 8)); static const struct gen7_sel_reg gen7_0_0_rb_rac_sel = { - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val = 0x0, }; static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = { - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val = 0x9, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h index 9bec75e830a3..7897622ea6f7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h @@ -478,14 +478,14 @@ static const u32 gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = { static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8)); static const struct gen7_sel_reg gen7_2_0_rb_rac_sel = { - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val = 0x0, }; static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = { - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val = 0x9, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h index 70805a5121be..20125d1aa21d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h @@ -1105,14 +1105,14 @@ static const u32 gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers[] = { static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers), 8)); static const struct gen7_sel_reg gen7_9_0_rb_rac_sel = { - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val = 0, }; static const struct gen7_sel_reg gen7_9_0_rb_rbp_sel = { - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val = 0x9, }; diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml index 369b96d7f7c9..3941e7510754 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -7,9 +7,11 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + + + + + - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + @@ -115,11 +222,16 @@ by a particular renderpass/blit. - + + + + + - + + - + b0..7 identifies where MRB data starts (and RB data ends) b8.15 identifies where VSD data starts (and MRB data ends) @@ -131,7 +243,7 @@ by a particular renderpass/blit. - + low bits identify where CP_SET_DRAW_STATE stateobj processing starts (and IB2 data ends). I'm guessing @@ -147,176 +259,293 @@ by a particular renderpass/blit. - - - - - + + + + + + + + - + - + + + + + + + + + + + - + + + + + + + - + - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - + + - + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + number of remaining dwords incl current dword being consumed? - - - number of remaining dwords incl current dword being consumed? - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + number of remaining dwords incl current dword being consumed? - + number of remaining dwords incl current dword being consumed? - - number of dwords that have already been read but haven't been consumed by $addr - - - + number of remaining dwords incl current dword being consumed? - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -342,22 +571,59 @@ by a particular renderpass/blit. - - - + + + - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + + + + + + + + + + @@ -376,49 +642,96 @@ by a particular renderpass/blit. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - - - - + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + - - - - - - - - - - - + + + + + + + + + + + + + + + @@ -610,6 +964,8 @@ by a particular renderpass/blit. + + @@ -638,72 +994,276 @@ by a particular renderpass/blit. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - Set to true when binning, isn't changed afterwards - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - - - - - + + + + + + + + + - + - - - + + + + + + + + + + + + + + + - - + + - - - - - - + + + + + + - - + + - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + @@ -712,30 +1272,66 @@ by a particular renderpass/blit. + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + + + + + + + + + @@ -803,10 +1399,14 @@ by a particular renderpass/blit. - - + + + + - + + + @@ -829,6 +1429,7 @@ by a particular renderpass/blit. + @@ -839,6 +1440,18 @@ by a particular renderpass/blit. + + + + + + + + + + + + @@ -853,6 +1466,7 @@ by a particular renderpass/blit. + @@ -860,9 +1474,7 @@ by a particular renderpass/blit. - - - + @@ -887,6 +1499,7 @@ by a particular renderpass/blit. + @@ -921,10 +1534,23 @@ by a particular renderpass/blit. + + + + + + + + + + + + + @@ -951,6 +1577,13 @@ by a particular renderpass/blit. + + + + + + + @@ -958,25 +1591,31 @@ by a particular renderpass/blit. + + + + + + @@ -984,16 +1623,25 @@ by a particular renderpass/blit. + + + + + + + + - + + @@ -1008,6 +1656,7 @@ by a particular renderpass/blit. + @@ -1022,10 +1671,16 @@ by a particular renderpass/blit. + + + + + + @@ -1073,7 +1728,6 @@ by a particular renderpass/blit. - @@ -1084,7 +1738,10 @@ by a particular renderpass/blit. - + + + + @@ -1123,6 +1780,28 @@ by a particular renderpass/blit. + + + + + + + Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have + GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass. + In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. + + + Disable LRZ feedback writes + + + + + + + + + + @@ -1130,6 +1809,7 @@ by a particular renderpass/blit. + @@ -1137,6 +1817,7 @@ by a particular renderpass/blit. + @@ -1158,13 +1839,21 @@ by a particular renderpass/blit. + + + + + + + + @@ -1176,14 +1865,26 @@ by a particular renderpass/blit. + + + + + + + + + + + + @@ -1203,6 +1904,7 @@ by a particular renderpass/blit. + @@ -1210,6 +1912,7 @@ by a particular renderpass/blit. + @@ -1217,8 +1920,10 @@ by a particular renderpass/blit. + + @@ -1226,6 +1931,7 @@ by a particular renderpass/blit. + @@ -1244,7 +1950,6 @@ by a particular renderpass/blit. - 0.0 if GREATER - 1.0 if LESS - @@ -1258,11 +1963,27 @@ by a particular renderpass/blit. Disable LRZ based on previous direction and the current one. If DIR_WRITE is not enabled - there is no write to direction buffer. - - + + + + + + + + + + The total size of the LRZ image array (not including + fast clear buffer), used as a stride for double + buffering used with concurrent binning. + + + + + + @@ -1275,14 +1996,17 @@ by a particular renderpass/blit. + + + @@ -1290,6 +2014,9 @@ by a particular renderpass/blit. + + + + + + + - - - - - - + + LUT used to convert quality buffer values to HW shading rate values. An array of 4-bit values. - + + - + + + + + + + + + + @@ -1372,7 +2109,7 @@ by a particular renderpass/blit. - + @@ -1391,7 +2128,7 @@ by a particular renderpass/blit. - + - + - - - - - + + + + + + + + + + + + + + + @@ -1462,7 +2219,8 @@ by a particular renderpass/blit. - + + @@ -1534,8 +2292,32 @@ by a particular renderpass/blit. - - + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -1546,11 +2328,17 @@ by a particular renderpass/blit. - + + + + + + + - - + + @@ -1613,7 +2401,9 @@ by a particular renderpass/blit. - + + + @@ -1627,14 +2417,15 @@ by a particular renderpass/blit. + + - - - + + @@ -1702,12 +2493,22 @@ by a particular renderpass/blit. - + + + + + + + + + + + @@ -1720,6 +2521,11 @@ by a particular renderpass/blit. + + + + + @@ -1798,8 +2604,10 @@ by a particular renderpass/blit. + + - + @@ -1814,12 +2622,30 @@ by a particular renderpass/blit. --> - + + + + + + + + + + + + + - + - - + + @@ -1849,9 +2675,19 @@ by a particular renderpass/blit. the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT. - - + + + + + + + + + + + + - + - + @@ -1963,7 +2799,7 @@ by a particular renderpass/blit. - + @@ -1972,26 +2808,40 @@ by a particular renderpass/blit. - + + + + + - + + + + + + + - - - - + + + + + + + - - + + + @@ -2014,6 +2864,10 @@ by a particular renderpass/blit. + + + + @@ -2028,6 +2882,9 @@ by a particular renderpass/blit. + + + @@ -2042,6 +2899,7 @@ by a particular renderpass/blit. + @@ -2051,6 +2909,7 @@ by a particular renderpass/blit. + @@ -2091,9 +2950,13 @@ by a particular renderpass/blit. + + + + @@ -2119,6 +2982,15 @@ by a particular renderpass/blit. + + Packed array of a6xx_varying_interp_mode + + + + Packed array of a6xx_varying_ps_repl_mode + + + @@ -2128,6 +3000,11 @@ by a particular renderpass/blit. + + + + + + + @@ -2181,13 +3061,23 @@ by a particular renderpass/blit. + + + + + + + + + + @@ -2211,6 +3101,10 @@ by a particular renderpass/blit. + + + + @@ -2231,6 +3125,7 @@ by a particular renderpass/blit. + - - - - + + + + + + + + + + - - - - + + + + + + + + + + @@ -2285,6 +3213,7 @@ by a particular renderpass/blit. + @@ -2292,10 +3221,13 @@ by a particular renderpass/blit. + + + @@ -2304,6 +3236,7 @@ by a particular renderpass/blit. + @@ -2311,12 +3244,19 @@ by a particular renderpass/blit. + + + + + + + @@ -2326,6 +3266,9 @@ by a particular renderpass/blit. + + + @@ -2333,6 +3276,7 @@ by a particular renderpass/blit. + + + + @@ -2381,7 +3329,13 @@ by a particular renderpass/blit. + + + + + + @@ -2391,24 +3345,37 @@ by a particular renderpass/blit. + + - - - - + + + + + + + + + + + + + + + @@ -2419,6 +3386,10 @@ by a particular renderpass/blit. + + + + @@ -2430,20 +3401,30 @@ by a particular renderpass/blit. + + + + + Written by CP_SET_VISIBILITY_OVERRIDE handler + - + - + + + - + + + @@ -2530,11 +3511,15 @@ by a particular renderpass/blit. - + - + + + + + - - @@ -2720,6 +3703,15 @@ by a particular renderpass/blit. + + Same on a6xx/a7xx, UMD should not need to write this + + + + UMD needs to write in some cases + + + @@ -2729,6 +3721,8 @@ by a particular renderpass/blit. + + @@ -2754,6 +3748,8 @@ by a particular renderpass/blit. + + @@ -2791,6 +3787,8 @@ by a particular renderpass/blit. + + @@ -2814,7 +3812,10 @@ by a particular renderpass/blit. - + + + + @@ -2843,6 +3844,8 @@ by a particular renderpass/blit. + + @@ -2886,13 +3889,19 @@ by a particular renderpass/blit. - + - + + + + + + + @@ -2993,13 +4002,11 @@ by a particular renderpass/blit. - + + - - - @@ -3036,6 +4043,7 @@ by a particular renderpass/blit. must be at least the actual CONSTLEN. + @@ -3047,7 +4055,8 @@ by a particular renderpass/blit. - + + @@ -3158,6 +4167,18 @@ by a particular renderpass/blit. + + + + + + + + + + + + - + - + + + + + @@ -3210,9 +4235,12 @@ by a particular renderpass/blit. --> + + + @@ -3234,22 +4262,27 @@ by a particular renderpass/blit. - - + + + - - + + - - - - + + + + + + + + - + @@ -3260,12 +4293,14 @@ by a particular renderpass/blit. - + - - - + + + + + @@ -3273,11 +4308,32 @@ by a particular renderpass/blit. - + + + - + + + + + + + + + + + + + + + + + + + + - - + + + + + @@ -3303,10 +4362,12 @@ by a particular renderpass/blit. - - + + + + @@ -3315,13 +4376,17 @@ by a particular renderpass/blit. + + + + @@ -3387,11 +4452,12 @@ by a particular renderpass/blit. + - - - + + + @@ -3404,7 +4470,7 @@ by a particular renderpass/blit. - + @@ -3414,8 +4480,13 @@ by a particular renderpass/blit. + + + + + @@ -3458,10 +4529,8 @@ by a particular renderpass/blit. - - - - + + @@ -3512,9 +4581,12 @@ by a particular renderpass/blit. - + + + + - + @@ -3718,7 +4790,7 @@ by a particular renderpass/blit. - + This register clears pending loads queued up by CP_LOAD_STATE6. Each bit resets a particular kind(s) of @@ -3741,10 +4813,30 @@ by a particular renderpass/blit. + + + This register clears pending loads queued up by + CP_LOAD_STATE6. Each bit resets a particular kind(s) of + CP_LOAD_STATE6. + + + + + + + + + + + + + + + @@ -3781,15 +4873,15 @@ by a particular renderpass/blit. - - - - + + + + - + @@ -3918,6 +5010,7 @@ by a particular renderpass/blit. + diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml index 4e42f055b85f..81538831dc19 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml @@ -303,7 +303,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml b/drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml new file mode 100644 index 000000000000..c842db8c78d6 --- /dev/null +++ b/drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml @@ -0,0 +1,299 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml index 06020dc1df44..79d204f1e400 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml @@ -11,6 +11,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml index 0e10e1c6d263..51e9c94f5e37 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml @@ -6,103 +6,102 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - - - - + + + + Flushes dirty data from UCHE, and also writes a GPU timestamp to the address if one is provided. - - - - - - - - - - + + + + + + + + + + - - - - - + + + + + If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main memory, skipping UCHE. - - + + Writes the GPU timestamp to the address that follows, once RB access and flushes are complete. - + - - - - + + + + - - - - - - - - - + + + + + + + + + Invalidates depth attachment data from the CCU. We assume this happens in the last stage. - + Invalidates color attachment data from the CCU. We assume this happens in the last stage. - + Flushes the small cache used by CP_EVENT_WRITE::BLIT (which, along with its registers, would be better named RESOLVE). - + Flushes depth attachment data from the CCU. We assume this happens in the last stage. - + Flushes color attachment data from the CCU. We assume this happens in the last stage. - + - 2D blit to resolve GMEM to system memory (skipping CCU) at the - end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for - more general blitting. + Triggers a resolve (GMEM to sysmem) or unresolve (sysmem to + GMEM) or clear blit, depending on CCU programming. - + Flip between the primary and secondary LRZ buffers. This is used for concurrent binning, so that BV can write to one buffer while BR reads from the other. - + Clears based on GRAS_LRZ_CNTL configuration, could clear @@ -115,44 +114,46 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> CUR_DIR_UNSET = 0x3 Clear of direction means setting the direction to CUR_DIR_UNSET. - - - - - - - - - - - + + + + + + + + + + + + Invalidates UCHE. - + - + Doesn't seem to do anything - - - - - - - - - - - - + + + + + + + + + + + - - + + + + @@ -310,11 +311,11 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> generate a VS|PS_done event - + generate a cache flush done event - + generate a z_pass done event - + not sure the real name, but this seems to be what is used for opencl, instead of CP_DRAW_INDX.. @@ -335,9 +336,9 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> load constant into chip and to memory load sequencer instruction memory (pointer-based) - + load sequencer instruction memory (code embedded in packet) - + load constants from a location in memory selective invalidation of state pointers @@ -662,6 +663,12 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + + + + + + @@ -1800,49 +1807,73 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + - - + + + + + + + + + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2066,6 +2097,14 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) payload *and* skipsaverestore is set. This is expected to restore static register values not saved when skipsaverestore is set. + + On BV, a skipsaverestore preemption is triggered + and this preamble type is executed whenever a + CP_THREAD_CONTROL that synchronizes threads + happens. This can be explicitly via + SYNC_THREADS, or implicitly when the value of + CONCURRENT_BIN_DISABLE changes from the previous + thread control. @@ -2308,5 +2347,99 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) + + + A7xx introduces the "resource table" which is managed by + CP_RESOURCE_LIST. It is used to synchronize BR and BV access + to resources such as LRZ buffers. + + The resource table consists of resources that are in-use by BR. + Each "resource" has a base address, which is + usually a pointer but is treated by the HW as an opaque handle, + a read/write bit, and a timestamp when it was last used. + Resources are removed from the table upon event completion when + a special CP_EVENT_WRITE::CLEAR_RENDER_RESOURCE bit is set, which + will remove all resources with a timestamp up to the current + timestamp. + + CP_RESOURCE_LIST first specifies a list of BV resources. For + each BV resource, the HW will check if there is a corresponding + BR resource in the table, and if at least one of the BV and BR + resources is marked WRITE then it will stall until the BR + resource is removed. + + It then specifies a list of BR resources. These will be added to + the resource table, unless there is an overflow in which case + the designated overflow register will have bit 0 set. Overflow + should cause the next binning pass to stall until BR is done, + effectively disabling concurrent binning. + + CP_RESOURCE_LIST must be executed by BV. BR resources are added + by BV and removed by BR. + + There is a separate table for "LRZ resources." These behave a + bit differently: specifying an LRZ resource via BV_RES_LRZ + stalls on any matching resource existing and then adds it to the + table, making it both a BV and BR resource in one. There is a + separate CLEAR_LRZ_RESOURCE bit for removing resources from the + LRZ table, and it only removes one resource given by a base + address passed to CP_EVENT_WRITE. Therefore timestamps are + unnecessary. + + + + What follows is a list of CP_BV_RESOURCE and then CP_RESOURCE_LIST_BR. + + + + + + BV resources don't go in the table. Instead CP waits until any + corresponding BR resources with the same base pointer are + finished before the packet completes. + + + + + INDIRECT resources are encoded as a 32b offset + 3b + bindless base selector. The offset is added to the given + BINDLESS_BASE pseudoregister and then the 64b value + fetched there is used as the pointer. + + + + + + + + + + + + + + + + + + + + What follows is a list of CP_BR_RESOURCE. + + + + + + + + + + + + + + + + -- 2.47.3