From 8d27dd0b219f00fc1e0548ae5008abd7bb350611 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Thu, 6 Nov 2025 10:01:08 -0700 Subject: [PATCH] cxl: Clarify comment in spa_maps_hpa() Update the comment in spa_maps_hpa() to clearly convey the construction of extended linear cache. Suggested-by: Dan Williams Link: https://lore.kernel.org/linux-cxl/68eea19c7e67e_2f899100a8@dwillia2-mobl4.notmuch/ Reviewed-by: Jonathan Cameron Reviewed-by: Gregory Price Link: https://patch.msgid.link/20251106170108.1468304-3-dave.jiang@intel.com Signed-off-by: Dave Jiang --- drivers/cxl/core/region.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index ccdb93f6d456..0482144200d8 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -851,9 +851,9 @@ static bool spa_maps_hpa(const struct cxl_region_params *p, return false; /* - * If an extended linear cache region then the CXL range is assumed - * to be fronted by the DRAM range in current known implementation. - * This assumption will be made until a variant implementation exists. + * The extended linear cache region is constructed by a 1:1 ratio + * where the SPA maps equal amounts of DRAM and CXL HPA capacity with + * CXL decoders at the high end of the SPA range. */ return p->res->start + p->cache_size == range->start && p->res->end == range->end; -- 2.47.3